1. Field of the Invention
The invention generally relates to integrated circuits (ICs) and in particular to techniques for limiting the current slew rate of output drivers of an IC.
2. Description of Related Art
Typical ICs include a set of output drivers for driving signals provided by internal circuitry of the IC through output pads onto output transmission lines, which may be individual lines of an output bus. A typical output driver includes one or more transistors connected to a high voltage power supply and ground. Gates of the transistors are connected to internal lines providing the signals to be output. Often, the output transistors are connected in "complementary" pairs, with each pair having a PMOS transistor and NMOS transistor. An output of the driver appears on interconnected drains of the NMOS and PMOS transistors.
In use, a signal to be output is simultaneously applied to the gates of each of the PMOS transistors and each of the NMOS transistors. Outputs from the transistors are combined onto the single output line. To provide sufficient power for pulling up or pulling down the output line, which may be subject to a large external load, the output driver is typically provided with fairly large transistors connected to a power supply providing a significant amount of charge. Accordingly, when the input signal is applied to the gates of transistors, a significant current is quickly conducted through the transistors. Noise in the output signal, however, is directly proportional to the time rate of change of current herein also referred to as the current "slew" rate. Accordingly, the faster the current increases from near 0 to an amount required for driving the output signal, the greater the noise in the output signal. Even greater noise occurs when the output signal is driven from high to low voltage. In this context, "noise" represents any deviation in the intended voltage of the output signal. If the deviation is significant, it may be difficult or impossible for an external device connected to the output line to properly receive the intended signal.
FIG. 1 illustrates the time rate of change of current drawn through the output transistors of such a conventional output driver. As can be seen, the current increases steeply than decreases steeply, resulting in a current spike 10, causing significant noise.
FIG. 2 illustrates a transition in an intended output signal 12 and an actual signal 14, subject to significant voltage noise. As can be seen, the output voltage varies or oscillates significantly, before being dampened. Large voltage swings, such as identified by reference 16, may be erroneously detected as a further transition in the output signal.
In practical systems, noise of the type illustrated in FIG. 2 occurs only if a large number of high-drive output drivers are triggered simultaneously causing a significant change in the total power supply current with respect to time. Accordingly, to avoid noise problems, many systems are merely configured to trigger only a certain maximum number of output drivers simultaneously, to thereby lower the overall time rate of change of current drawn from the power source and to thereby limit the amount of noise. For state of the art integrated circuits, however, it is frequently necessary to trigger a large number of output drivers simultaneously for use in, for example, driving a 32-bit bus at a high dock rate. Accordingly, techniques have been developed for reducing the current slew rate within at least some of the output drivers to allow a large number of the drivers to be triggered simultaneously while generating an acceptable amount of voltage noise.
FIG. 3 illustrates the PMOS components of a conventional output driver configured to reduce the current slew rate. Output driver 20 includes a set of three separate output transistors 22, 24 and 26 interconnected to a set of three staggered inverters 28, 30 and 32. An input line 34 is connected into inputs of each of the inverters. An output of inverter 28 enables inverter 30. Likewise, an output of inverter 30 enables inverter 32. Accordingly, the three inverters output three versions of the input signal (inverted) with each being delayed or advanced with respect to the others.
The outputs of the three inverters are connected to the gates of transistors 22 through 26, respectively, such that three transistors are triggered at slightly different times. More specifically, transistor 26 is triggered first, then transistor 24, and finally transistor 22. By triggering the output transistors at slightly different times, the total time rate of change of current caused by activation of the output transistors is decreased, thus yielding lower voltage noise.
Although not shown, output driver 20 also includes a set of NMOS transistors and a set of corresponding staggered inverters, interconnected as a mirror image of the components shown in FIG. 2. Also, although not separately shown, each of transistors 22, 24 and 26 may represent an entire set of transistors. In other words, a set of, for example, four or five output transistors may be connected to the outputs of each of the inverters. Such may be required if the individual transistors are fairly small in size. In a practical system, only some of the output drivers are configured as shown in FIG. 2. Other output drivers, particularly those transmitting critical signals, are configured conventionally. Such allows the critical signals to be transmitted promptly, while only the less critical signals are delayed somewhat by transmission through a set of staggered inverters.
The configuration of FIG. 2 succeeds in reducing the current slew rate caused by signals transmitted therethrough. However, one disadvantage of the arrangement of FIG. 3, is that the slew rate, once set, cannot be modified. In other words, during design of an IC incorporating the output driver of FIG. 3, the sizes and characteristics of the inverters and transistors must be determined. Often, however, it is not known during the design stage what the slew rate should be set to. For example, the speed of operation of components within integrated circuit are highly dependent upon temperature. Accordingly, if an IC is to be used in a low temperature environment, the output drivers will switch faster, resulting in higher noise. However, during the design stage, it may not be known whether the IC is to be used in a low temperature environment or not. Also, it is often not known what peripheral components the IC will be used in connection with. The peripheral components may affect the external load applied to the output buffers, and thereby affect the amount of voltage noise occurring for a given current slew rate. Also, ICs fabricated in accordance with a single design may be operated at different clock rates. For those with slow clock rates, less 20 voltage noise is generated than ICs employed with higher clock rates. The amount of voltage noise may also depend upon the packaging of the IC or upon its form factor.
Because the environment, clock rate, packaging or form factor of an IC may not be known in advance, a system designer must "guess" or otherwise predict what amount of current slew rate reduction is required and design the IC accordingly. The designer must also allow for a sufficient noise margin in the event that the current slew rate reduction is not sufficient. Such can result in an overall IC configured to perform at a clock rate less than would otherwise be desired.
Accordingly, it would be desirable to provide a method and apparatus for controlling current slew rate within an output driver wherein the current slew rate can be set or modified subsequent to wafer fabrication, and perhaps subsequent to packaging of the wafer in an IC and it is to that end that the aspects of the present invention are drawn.